This invention relates to a switch interface circuit and in particular to a switch interface circuit for control of gate voltage on a power metal oxide semiconductor field effect transistor (MOSFET) device.
A P-channel power MOSFET is ideally suited for use as a high voltage, high current switch where the source of the MOSFET is connected to a positive power supply and the drain of the MOSFET is connected to a load such as a motor, which in turn is referenced to ground, either through another MOSFET or directly. When a P-channel power MOSFET is used in this application, the gate of the MOSFET is driven negative with respect to the source in order to turn on the device. Using an N-channel power MOSFET in this application requires a second power supply, more positive than the first power supply, to bias the N-channel MOSFET gate in order to turn on the MOSFET. Despite the advantage of the negative gate threshold voltage of a P-channel MOSFET, problems remain in the design of an ideal high voltage gate drive circuit.
An ideal gate drive circuit would provide a short circuit between the power MOSFET gate and source when the power MOSFET is turned off, in order to eliminate the possibility of spurious (e.g., dV/dt induced) power MOSFET turn-on. The ideal gate drive circuit would consume zero standby current when the power MOSFET is turned on and when the power MOSFET is turned off. The ideal gate drive circuit would provide sufficient gate drive current during turn-on of the power MOSFET to achieve rapid switching and low switching power losses. The ideal gate drive circuit would limit the gate-to-source voltage of the power MOSFET to a value less than the breakdown voltage of the gate oxide. The ideal gate drive circuit would also provide isolation for, and easy connection to, low voltage logic circuits.
The simplest gate drive circuit is a resistor, in parallel with a Zener diode, connected between the gate and source of the P-channel power MOSFET. This circuit can be interfaced to low voltage logic by means of a switched current source connected between the gate of the power MOSFET and ground. Disadvantages of this circuit are the incompatible requirements of a low resistance between gate and source of the power MOSFET to reduce the possibility of dV/dt-induced turn-on of the power MOSFET when the power MOSFET is off, and a high resistance between the gate and source of the power MOSFET to reduce power dissipation when the power MOSFET is on. However, this circuit does consume zero power when the power MOSFET is turned off, allows high-current turn-on pulses, and limits the gate voltage of the power MOSFET to a safe value.
More complicated gate drive circuits include a low voltage negative power supply referenced to the high voltage power supply. This type of special power supply has been used to power logic circuits that drive the gate of the power MOSFET. Interface with ground-referenced low voltage logic has been provided by light-coupled circuits, such as opto couplers. This type of circuitry has many of the features desired in the gate drive circuit; however, circuit complexity and high cost are distinct disadvantages.